The present invention relates to a highly reliable and highly efficient DC converter.
FIG. 1 is a circuit configuration diagram of a conventional DC converter, which is disclosed in Japanese Patent Application Laid-Open No. JP2000-92829. The DC converter shown in FIG. 1 employs an active-clamp topology, and includes a bridge circuit BD that rectifies an AC voltage supplied from an AC power supply Vac and also a capacitor C1 that smoothes outputs of the bridge circuit BD. A series circuit of a primary winding P1 (the number of turns is Np) of a transformer T and a MOSFET (hereinafter, FET) operable as a main switch Q1 is connected to both ends of the capacitor C1. A voltage across the capacitor C1 is an input voltage Vin.
A series circuit of an FET and the like operable as an auxiliary switch Q2 and a capacitor C2 is connected to both ends of the primary winding P1 of the transformer T. The main switch Q1 and the auxiliary switch Q2 are turned ON/OFF alternately by PWM control of a control circuit 111.
A secondary winding S1 (the number of turns is Ns) of the transformer T has a winding structure to generate a voltage in phase with that of the primary winding P1 of the transformer T. A rectifying and smoothing circuit having diodes D10 and D11, a reactor L10, and a capacitor C10 is connected to this secondary winding S1. This rectifying and smoothing circuit rectifies and smoothes a voltage induced in the secondary winding S1 of the transformer T (ON/OFF-controlled pulse voltage), and supplies a DC output to a load 30.
An auxiliary winding S2 (the number of turns is NA) of the transformer T has a winding structure to generate a voltage in opposite phase to that of the primary winding P1 of the transformer T. A rectifying and smoothing circuit which has a diode D1 and a capacitor C3 is connected to this auxiliary winding S2. This rectifying and smoothing circuit rectifies and smoothes a voltage induced in the auxiliary winding S2 of the transformer T, and supplies an obtained DC voltage to the control circuit 111 as a voltage Vcc.
The control circuit 111 generates a Q1 control signal Q1c having a pulse for controlling ON/OFF of the main switch Q1 and a Q2 control signal Q2c having a pulse for controlling ON/OFF of the auxiliary switch Q2 (Q2 control signal Q2c has an inverted phase to the Q1 control signal Q1c) based on an error voltage supplied from an error detector 40 (a difference voltage between an output voltage Vo and a reference voltage), and controls duty ratios of the Q1 control signal Q1c and the Q2 control signal Q2c so that the output voltage Vo becomes a predetermined value.
The DC converter further includes a low side driver 112 and a high side driver 113. The low side driver 112 generates a Q1 gate signal Q1g by amplifying the Q1 control signal Q1c of the control circuit 111, and applies the Q1 gate signal Q1g to the gate of the main switch Q1 to activate it. The high side driver 113 generates a Q2 gate signal Q2g by amplifying the Q2 control signal Q2c of the control circuit 111, and applies the Q2 gate signal Q2g to the gate of the auxiliary switch Q2 to activate it.
Operations of the DC converter thus configured will be described next with reference to timing charts shown in FIGS. 2 to 5.
Assuming that the duty ratio of the main switch Q1 (a percentage where the main switch Q1 is ON) is D (0<D<1), the output voltage Vo can be given by the following expression (1),Vo=Vin(Ns/Np)D  (1).
Since a voltage applied to the primary winding P1 of the transformer T while the main switch Q1 is ON is equal to a voltage applied to the primary winding P1 of the transformer T while the auxiliary switch Q2 is OFF, we have the following expression (2),Vin·D=Vc(1−D)  (2).
Since the expression (2) can be arranged as,Vc=Vin·D/(1−D)  (3).
Referring to the expression (1), we find that,D=(Vo/Vin)·(Np/Ns)  (4).
Accordingly, the voltage Vc across the capacitor C2 is determined, using the expressions (3) and (4), by a following expression,Vc=(Vo·(Np/Ns))/(1−(Vo/Vin)·(Np/Ns))  (5).
This expression is based on the premise that a relationship of 0<(Vo·Np)/(Vin·Ns)<1 is satisfied. Therefore, the voltage Vc increases with decreasing input voltage Vin.
FIGS. 2 and 3 are waveform diagrams for explaining the relationship between the input voltage Vin and the voltage Vc across the capacitor C2 in the conventional DC converter. FIG. 2 shows an operational waveform when the input voltage Vin is high, and FIG. 3 shows an operational waveform when the input voltage Vin is low.
As shown in FIG. 2, when the input voltage Vin is high, for example, 375V, an ON-period of the main switch Q1 (a period for which a drain-source voltage Vds indicates L-level) becomes short in order to obtain, for example, an output voltage Vo of 24V and an output current of 10A. During the ON-period of the main switch Q1, a drain current Id flows into the main switch Q1 through the primary winding P1 of the transformer T. In this case, the voltage Vc across the capacitor C2 is about 100V.
On the other hand, as shown in FIG. 3, when the input voltage Vin is low, for example, 100V, the ON-period of the main switch Q1 becomes long in order to obtain, for example, an output voltage Vo of 24V and an output current of 10A. In this case, the voltage Vc across the capacitor C2 is about 370V, which is high.
Consequently, when the supply from the AC power supply Vac is stopped at time t1 in the DC converter shown in FIG. 1, envelope waveforms (loci of the maximum values of each waveform) become as shown in FIG. 4, where the input voltage Vin decreases gradually, and the voltage Vc across the capacitor C2 increases gradually. Accordingly, the voltage Vcc generated at the auxiliary winding S2, the diode D1, and the capacitor C3 decreases. When the voltage Vcc reaches a stop voltage of the control circuit 111 at time t2, the control circuit 111 stops, and then the main switch Q1 and the auxiliary switch Q2 become an OFF-state. Therefore, the discharge path of the capacitor C2 is eliminated, so that a large voltage Vc is held across the capacitor C2.
In this state, when the AC power supply Vac is turned on again and the input voltage Vin is reapplied, the voltage Vcc increases through a starting resistor R1 operable as an activator, and when the voltage Vcc reaches an activation voltage of the control circuit 111, the main switch Q1 and the auxiliary switch Q2 start switching operations such that they are turned ON/OFF alternately. At this time, envelope waveforms (loci of the maximum values of each waveform) become as shown in FIG. 5. When the auxiliary switch Q2 is turned on at time t3, a voltage of [Vc+Vin], which is the sum of the high voltage Vc being held at the capacitor C2 and the input voltage Vin, is applied to the main switch Q1. That is, a large voltage which is not applied in a steady state is applied to the main switch Q1, and therefore a device with a high withstand voltage must be used for the main switch Q1 to prevent damage thereto.